The present invention relates to a semiconductor memory, and more particularly to a semiconductor memory device which has a high packaging density and which is advantageous for attaining a fast operation as well as a high S/N (signal-to-noise) ratio.
As a semiconductor memory has its packaging density rendered higher and its storage capacity larger, the capacity of a charge storage portion in each memory cell decreases. On the other side, the area of a memory array on a memory chip increases, and the capacitance of a data line, the length thereof, etc. increase. Accordingly, it becomes increasingly difficult to hold the features of fast operation and high S/N ratio.
In order to obtain a large-capacity memory of fast operation and high S/N ratio, various contrivances have hitherto been made. An example will be described on a MOS dynamic memory which is constructed of memory cells each including one transistor and one capacitor.
In the example of FIG. 1, two memory arrays MA1 and MA2 are arranged on both the sides of a circuit block Y DEC which includes a Y decoder and drivers and have sense amplifiers SA arranged on the outer sides thereof. When a memory cell MC connected to a data line D.sub.0 is selected by a circuit block X DEC which contains an X decoder and drivers, a dummy cell DC connected to a data line D.sub.0 adjoining the data line D.sub.0 is selected, the difference between the potentials of the data lines D.sub.0 and D.sub.0 as based on the difference of the capacitances of both the cells is amplified by the sense amplifier SA, and reading is effected through common input/output lines I/O and I/O. In this manner, in the example of FIG. 1, the pair of data lines which are differentially read out are arranged in adjacency to each other, to form the so-called folded data line arrangement. Therefore, the example has the merit that noise attributed to the electrical unbalance of the data lines does not develop in any substantial amount. However, when the area of the memory array becomes large with an increase in the storage capacity, the capacitance of the data line increases, so that a read-out voltage decreases. When, in this regard, the data line is shortened by increasing the number of divided memory arrays into, e.g., four memory arrays or eight memory arrays, it is possible to increase the read-out voltage and to raise the writing speed. Since, however, one Y decoder needs to be disposed for every two memory arrays and one set of common input/output lines or one sense amplifier needs to be disposed for every memory array, these peripheral circuits bring about the disadvantage of a large occupying area.